Hi,
Pleasure mailing you. Please go through the below requirement and let me know if you are comfortable for the position.
Please send me your updated resume along with the best hourly rate, work authorization status and availability.
An early response is really appreciated
Role : Senior Analog and mixed-signal engineer
Location : Remote
Duration : 9 Months
Experiences required
· Degree in electrical engineering (microelectronics or nanoengineering or physics ).
· Extensive industrial experience in analog and mixed-signal design (15+yr).
· Solid knowledge of semiconductor physics and the physical behavior of transistors.
· Academic and/or professional background in nanoscience with specific focus on semiconductor physics
· Strong background on physics of semiconductor technology and the application of it towards building analog electronic circuits.
· Understanding of semiconductor process, gradients, variability
Mandatory competencies
• Language: Fluency in English, both written and spoken.
• Problem-solving skills: Able to solve problems and implement solutions autonomously.
• Social skills: Able to work in a team.
• Able to do high-level system definition and derive block-level specification, based on the optimal performance trade-offs.
• Able to support the verification team in debugging measurement and/or yield issues.
• You have the drive to share your knowledge and look across teams to improve overall quality and execution.
Key Technical Skillset required for this program
- Good experience in FinFet technologies such as 5nm, 7nm, 16nm , <22nm
- Analog Mixed Signal, Oscillator array in CMOS, PLL, precision analog, highly sensitive in VCO parasitics, variability uncertainty, Monte Carlo. Need to be aware to circuit statistical variant analysis
- The design problem is not only functionality but to design variants across 10 years lifetime. The circuits will be used to generate an encryption key. Aging effects, reliability effects will impact variance of encryption key
- very detailed rigorous in analyzing – understanding chip level process or IR gradients – should be aware of systematic effect so that gradient introduced in randomization doesn’t break the reliability of the encryption key
- Knows effect of parasitics, variability, monte carlo and knowledge device physics
- PLL designer who can understand lifetime statistical variance, reliability issues
Key responsibilities
- Contribute to the successful realization of a project in a design team.
- Autonomously design a given topology to meet the given specifications in the foreseen timeframe.
- Support other design engineers in handling complex design issues.
- Achieve the successful realization of the layout in close collaboration with the layout team.
- Share design experiences with co-developers and/or other designers.
- Support the project leader in the definition phase and during the design phase as a technical lead.
- Lead teams, set priorities, timelines, and meet milestones.
- Perform high-level system verifications and support the Verification engineer in debugging.
- Collaborate across teams for seamless integration of analog and digital components.
- Contribute to the achievement of the quality objectives as stated in the quality policy.
Quality
- Commit to complying with the requirements of the Quality Management System that are related to the job title and to possible changes of the system.
- Commit to developing and implementing Quality Management System and continually improving its effectiveness
Report to
- Project leader
- Analog design team leader
Tools:
Designer:
- Virtuoso Schematic Editor
- Assembler/Explorer/ADE(XL)
Thanks,
Suresh Kumar Reddy K
Lead - US IT
Email : sureshr@tekskillsinc.com | www.tekskillsinc.com
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